Vertical field effect transistor including extension and stressors

ABSTRACT

A vertical field effect transistor (FET) includes a first source/drain region formed on an upper surface of a semiconductor substrate, and a semiconductor channel material that extends vertically from the first source/drain region to a second source/drain region. A metal gate structure encapsulating the semiconductor channel material. The vertical FET further includes a stressor region that contacts the semiconductor channel material and the first source/drain region. The combination of the semiconductor channel material and the stressor region defines a total length of a strained channel region of the vertical field effect transistor.

BACKGROUND

The present invention relates to field effect transistors (FETs), andmore specifically, to vertical-type FETs.

As demands to reduce the dimensions of transistor devices continue, newdesigns and fabrication techniques to achieve a reduced device footprintare developed. Vertical-type field effect transistors (vertical FETs)have recently been developed to achieve a reduced FET device footprintwithout comprising the necessary FET device performance. Vertical FETsare fabricated such that source/drain (S/D) regions are arranged atopposing ends of a vertical channel region.

The vertical orientation of the vertical FET allows for controlling thevoltage rating as a function of the doping and thickness of theepitaxial layer, while the current rating is controlled as a function ofthe channel width. Accordingly, a vertical FET may sustain both highblocking voltage and high current within a compact semiconductorsubstrate (e.g., silicon substrate). Vertical FETs may also allow forrelaxed gate lengths to better control device electrostatics, withoutsacrificing the gate contact pitch size.

SUMMARY

According to a non-limiting embodiment of the present invention, avertical field effect transistor (FET) includes a first source/drainregion formed on an upper surface of a semiconductor substrate, and asemiconductor channel material that extends vertically from the firstsource/drain region to a second source/drain region. A metal gatestructure encapsulating the semiconductor channel material. The verticalFET further includes a stressor region that contacts the semiconductorchannel material and the first source/drain region. The combination ofthe semiconductor channel material and the stressor region defines atotal length of a strained channel region of the vertical field effecttransistor.

According to another non-limiting embodiment, a method of inducing astrain on a channel region of a vertical field effect transistor (FET)comprises removing an encapsulating structure to form a void thatexposes a first portion of the channel region. The channel region has afirst lattice constant. The method further includes selectively removingthe first portion of the channel region while preserving a secondportion of the channel region. The second portion has a first channelend connected to a first source/drain region and a second channel endexposed to the void. The method further includes forming a stressorregion having a first stressor end formed against the second channel anda second stressor end formed against a second source/drain region. Thestressor region has a second lattice constant different from the firstlattice constant so as to induce a strain on the preserved secondportion of the channel region.

According to yet another non-limiting embodiment, a method of inducingstrain on a channel region of a vertical transistor comprises forming achannel region that extends from a first source/drain region to a secondsource/drain region, and encapsulating a first portion of the channelregion with a first encapsulating structure and a second portion of thechannel region with a second encapsulating structure. The method furthercomprises removing the second encapsulating structure while maintainingthe first encapsulating structure to expose the second portion of thechannel region, and replacing the second portion of the channel regionwith a stressor region that induces a strain on the first portion of thechannel region.

Additional features are realized through the techniques of the presentinvention. Other embodiments are described in detail herein and areconsidered a part of the claimed invention. For a better understandingof the invention with the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other features of the invention areapparent from the following detailed description taken in conjunctionwith non-limiting embodiments illustrated in the accompanying drawings.FIGS. 1A-20 are a series of views illustrating a method of forming avertical FET device according to exemplary embodiments of the presentteachings, in which:

FIGS. 1A-1B are a cross-sectional side view and a top view,respectively, of a starting semiconductor structure according to anon-limiting embodiment;

FIGS. 2A-2B illustrate the semiconductor structure of FIGS. 1A and 1Bafter forming a trench through the dielectric capping layer, a dummygate layer, a counter-dielectric layer, and a lower intermediate spacerto expose a heavily-doped S/D layer;

FIGS. 3A-3B illustrate the semiconductor structure of FIGS. 2A-2Bfollowing an oxidation process that oxidizes a portion of the dummy gatesidewalls;

FIGS. 4A-4B illustrate the semiconductor structure of FIGS. 3A-3B afterperforming an epitaxial growth process that fills the trench with asemiconductor material to form a channel region;

FIGS. 5A-5B illustrate the semiconductor structure of FIGS. 4A-4B afterpartially recessing the epitaxial layer, and re-filling the trench withan upper dielectric material;

FIGS. 6A-6B illustrate the semiconductor structure of FIGS. 5A-5Bfollowing a selective etching process to remove the dielectric cappinglayer, and after performing an epitaxial growth process to grow an upperS/D region from the channel region;

FIGS. 7A-7B illustrate the semiconductor structure of FIGS. 6A-6Bfollowing a spacer deposition process that forms spacers on an outersurface of the upper source/drain region and the upper dielectricmaterial;

FIGS. 8A-8B illustrate the semiconductor structure of FIGS. 7A-7Bfollowing a selective etching process that etches a portion of the upperspacer and a portion of the dummy gate layer while stopping on an uppersurface of the lower intermediate spacer;

FIGS. 9A-9B illustrate the semiconductor structure of FIGS. 8A-8B afterperforming a selective etching process to remove remaining portions ofthe dummy gate;

FIG. 10 illustrates the semiconductor structure of FIGS. 9A-9B afterremoving the oxide sidewall portions, depositing a channel dielectricmaterial and a work function metal layer on sidewalls of the channelregion and the S/D spacers, and selectively etching the portions of thechannel dielectric material and work function metal layer away from theS/D spacers;

FIG. 11 illustrates the semiconductor structure of FIG. 10 following ametal deposition process that deposits a metal gate material thatencapsulates the channel dielectric material, a work function metallayer, and channel region;

FIG. 12 illustrates the semiconductor structure of FIG. 11 following agate lithography and etching process that forms a gate structure andexposes an upper surface of the upper intermediate spacer layer;

FIG. 13 illustrates the semiconductor structure of FIG. 12 followingdeposition of an inter-layer dielectric (ILD) material on an uppersurface of the upper intermediate spacer layer to surround the metalgate structure and the S/D spacers;

FIG. 14 illustrates the semiconductor structure of FIG. 13 following alithography and patterning process to form a first S/D trench thatextends through the ILD material and the upper intermediate spacer layerand into the intermediate dielectric layer;

FIG. 15 illustrates the semiconductor structure of FIG. 14 following aselective etching process to selectively remove the intermediatedielectric layer while maintaining the upper and lower intermediatespacers and the channel region;

FIG. 16 illustrates the semiconductor structure of FIG. 15 following aselective etching process that removes a portion of the channel regionwhile maintaining the upper and lower intermediate spacers;

FIG. 17 illustrates the semiconductor structure of FIG. 16 following achannel sigma etching process that forms self-limiting cavities in thechannel region and the heavily-doped S/D layer;

FIG. 18 illustrates the semiconductor structure of FIG. 17 followingformation of a stressor region between the channel region and theheavily-doped S/D region;

FIG. 19 illustrates the semiconductor structure of FIG. 18 following alithography and patterning process to form a first contact trench thatextends through the ILD material and into a metal gate structure, and asecond contact trench between the upper spacers that exposes the upperS/D region; and

FIG. 20 illustrates the semiconductor structure of FIG. 19 after fillingthe first S/D trench, the gate trench and the second S/D trench with ametal material form a first S/D contact, a gate contact, and a secondS/D contact.

DETAILED DESCRIPTION

Various embodiments of the present disclosure are described herein withreference to the related drawings. Alternative embodiments may bedevised without departing from the scope of this disclosure. It is notedthat various connections and positional relationships (e.g., over,below, adjacent, etc.) are set forth between elements in the followingdescription and in the drawings. These connections and/or positionalrelationships, unless specified otherwise, may be direct or indirect,and the present disclosure is not intended to be limiting in thisrespect. Accordingly, a coupling of entities may refer to either adirect or an indirect coupling, and a positional relationship betweenentities may be a direct or indirect positional relationship. As anexample of an indirect positional relationship, references in thepresent disclosure to forming layer “A” over layer “B” includesituations in which one or more intermediate layers (e.g., layer “C”) isbetween layer “A” and layer “B” as long as the relevant characteristicsand functionalities of layer “A” and layer “B” are not substantiallychanged by the intermediate layer(s).

The term “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any embodiment or design described herein as“exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or designs. The terms “at least one”and “one or more” may be understood to include any integer numbergreater than or equal to one, i.e. one, two, three, four, etc. The terms“a plurality” may be understood to include any integer number greaterthan or equal to two, i.e. two, three, four, five, etc. The term“connection” may include both an indirect “connection” and a direct“connection.”

For the sake of brevity, conventional techniques related tosemiconductor device and IC fabrication may not be described in detailherein. Moreover, the various tasks and process steps described hereinmay be incorporated into a more comprehensive procedure or processhaving additional steps or functionality not described in detail herein.In particular, various steps in the manufacture of semiconductor devicesand semiconductor-based ICs are well known and so, in the interest ofbrevity, many conventional steps will only be mentioned briefly hereinor will be omitted entirely without providing the well-known processdetails.

By way of background, however, a more general description of thesemiconductor device fabrication processes that may be utilized inimplementing one or more embodiments of the present disclosure will nowbe provided. Although specific fabrication operations used inimplementing one or more embodiments of the present disclosure may beindividually known, the disclosed combination of operations and/orresulting structures of the present disclosure are unique. Thus, theunique combination of the operations described in connection with thefabrication of a coupler system according to the present disclosureutilize a variety of individually known physical and chemical processesperformed on a semiconductor (e.g., silicon) substrate. In general, thevarious processes used to form a micro-chip that will be packaged intoan IC fall into three categories, namely, film deposition, patterning,etching and semiconductor doping. Films of both conductors (e.g.,poly-silicon, aluminum, copper, etc.) and insulators (e.g., variousforms of silicon dioxide, silicon nitride, etc.) are used to connect andisolate transistors and their components. Selective doping of variousregions of the semiconductor substrate allows the conductivity of thesubstrate to be changed with the application of voltage. By creatingstructures of these various components, millions of transistors can bebuilt and wired together to form the complex circuitry of a modernmicroelectronic device.

Fundamental to all of the above-described fabrication processes issemiconductor lithography, i.e., the formation of three-dimensionalrelief images or patterns on the semiconductor substrate for subsequenttransfer of the pattern to the substrate. In semiconductor lithography,the patterns are a light sensitive polymer called a photo-resist. Tobuild the complex structures that make up a transistor and the manywires that connect the millions of transistors of a circuit, lithographyand etch pattern transfer steps are repeated multiple times. Eachpattern being printed on the wafer is aligned to the previously formedpatterns and slowly the conductors, insulators and selectively dopedregions are built up to form the final device.

Turning now to a more detailed discussion of one or more embodiments,fabrication of vertical FETs can be challenging because the verticalorientation causes variations in the gate length, spacer thickness andextension doping profile. Additionally, introducing strain in verticalFETs is also challenging because of the inherently relaxed channelmaterial due to its vertical pillar-like geometry.

Various non-limiting embodiments of the invention utilize a sigma-etchedchannel region near the bottom terminal of the vertical FET so as toreduce the variations seen in conventional vertical FET fabricationprocesses. In addition, various non-limiting embodiments of theinvention include an extension region, which allows for applying astrain to the channel region. The strain may be achieved by embedding anepitaxially grown stressor region between the channel region and theheavily doped source/drain region. The stressor region has a differentlattice constant compared to the channel region material, which inducesa strain (e.g., compressive or tensile) upon the channel region, therebyimproving hole (or electron) mobility of the vertical FET.

With reference now to FIGS. 1A-1B, starting semiconductor structure 100is illustrated according to a non-limiting embodiment. The startingsemiconductor structure 100 extends along a first axis (e.g., a Z-axis)to define a vertical height, a second axis (e.g., an X-axis) to define adistance of a first side (i.e., a first side distance), and a third axis(Y-axis) to define a distance of a second side (i.e., a second sidedistance). A cross-section of the starting semiconductor structure 100illustrated in FIG. 1B illustrates a plurality of regions 10-40 stackedatop a semiconductor substrate 101.

The semiconductor substrate 101 may include a bulk semiconductor (Si)substrate 101 or a semiconductor-on insulator substrate 101. Thesemiconductor material of the substrate 101 includes varioussemiconductor materials including, but not limited to, silicon (Si).

The plurality of stacked regions includes, a first S/D region 10 formedatop the semiconductor substrate 101, an intermediate dielectric region20 formed atop the first S/D region 10, a sacrificial gate region 30formed atop the intermediate dielectric region 20, and a capping region40 formed atop the sacrificial gate region 30.

The first S/D region 10 includes a counter-doped layer 102 interposedbetween a heavily-doped source/drain layer 103 (e.g., a heavily dopedsource layer 103) and the semiconductor substrate 101. In at least oneembodiment, the counter-doped layer 102 is formed directly on an uppersurface of the semiconductor substrate 101, and the heavily-doped sourcelayer 103 formed directly on the upper surface of the counter-dopedlayer 102. The heavily-doped source layer 103 and the counter-dopedlayer 102 are formed on the semiconductor substrate 101 by incorporatingdopants into the semiconductor substrate 101 or forming an epitaxialgrowth layer on the semiconductor substrate 101. The heavily-dopedsource layer 103 is heavily doped with a dopant, which may be a p-typedopant (e.g., boron or gallium) or an n-type dopant (e.g., phosphorus orarsenic).

The counter-doped layer 102 includes a dopant that is different/oppositethan the dopant in the heavily-doped source layer 103. For example, whenthe heavily-doped source layer 103 includes a p-type dopant, thecounter-doped source layer 102 includes an n-type dopant, and when theheavily-doped source layer 103 includes an n-type dopant, thecounter-doped source layer 102 includes a p-type dopant. Theheavily-doped source layer 103 is heavily doped, including a dopantconcentration in a range from about 10¹⁹ to about 10²² atoms/cm³. Thevertical thickness of the counter-doped source layer 102 may be in arange from about 5 to about 50 nanometers (nm), or from about 10 toabout 20 nm. The vertical thickness of the heavily-doped source layer103 may be in a range from about 50 to about 250 nm, or from about 100to about 200 nm.

The intermediate dielectric region 20 includes an intermediatedielectric layer 112 interposed between a first spacer 110 a (e.g., alower intermediate spacer 110 a) and a second spacer 110 b (e.g., anupper intermediate spacer 110 b). The intermediate dielectric layer 112comprises a dielectric material different from the dielectric materialof the intermediate spacers 110 a-110 b. The dielectric layer 112 mayhave a vertical thickness ranging, for example, from about 10 nm toabout 100 nm.

The lower intermediate spacer 110 a may be formed as a blanket layerover the heavily-doped source layer 103, and the upper intermediatespacer 110 b may be formed as a blanket layer over the dielectric layer112. The intermediate spacers 110 a-110 b may have a vertical thicknessranging, for example, from about 3 to about 15 nm. In anotherembodiment, the first spacer 110 a may have a vertical thickness in arange from about 5 to about 10 nm.

In at least one embodiment, the intermediate spacers 110 a-110 b maycomprise a material that has a relative dielectric constant value (e.g.,k-value) of about 7-8. In other embodiments, the intermediate spacers110 a-110 b include a material with a k-value of at least 7 or at least8. The intermediate spacers 110 a-110 b and the intermediate dielectriclayer 112 may be deposited by various processes including, but notlimited to, chemical vapor deposition (CVD) or physical vapor deposition(PVD). In at least one embodiment, the lower and upper intermediatespacers 110 a-110 b comprise silicon nitride (SiN) while theintermediate dielectric layer 112 comprises boron nitride (BN). In thismanner, the intermediate dielectric layer 112 may be selectively etchedwith respect (i.e., while maintaining) to one or more of theintermediate spacers 110 a-110 b as discussed in greater detail below.

The sacrificial gate region 30 includes a dummy gate 120 that is formedon an upper surface of the upper intermediate spacer 110 b. The dummygate 120 includes a sacrificial gate material, for example, amorphoussilicon (aSi) or polycrystalline silicon (polysilicon). The sacrificialmaterial may be deposited by a deposition process, including, but notlimited to, physical vapor deposition (PVD), chemical vapor deposition(CVD), plasma enhanced chemical vapor deposition (PECVD), inductivelycoupled plasma chemical vapor deposition (ICP CVD), or any combinationthereof. The sacrificial material forming the dummy gate 120 has avertical thickness, for example, ranging from about 10 nm to about 40nm.

The capping region 40 includes a capping spacer 111 that is formed on anupper surface of the dummy gate 120, and a dielectric capping layer 130that is formed on an upper surface of the capping spacer 111. Thecapping spacer 111 may be formed of an insulating material including,but not limited to, silicon dioxide, silicon nitride, SiOCN, or SiBCN.Other non-limiting examples of materials for the capping spacer 111include dielectric oxides (e.g., silicon oxide), dielectric nitrides(e.g., silicon nitride), dielectric oxynitrides, or any combinationthereof. The capping spacer 111 may have a vertical thickness ranging,for example, from about 3 nm to about 15 nm.

The dielectric capping layer 130 may comprise various dielectricmaterials including, but not limited to, silicon dioxide (SiO₂),tetraethylorthosilicate (TEOS) oxide, high aspect ratio plasma (HARP)oxide, high temperature oxide (HTO), high density plasma (HDP) oxide,oxides (e.g., silicon oxides) formed by an atomic layer deposition (ALD)process, or any combination thereof. The dielectric capping layer 130has a vertical thickness in ranging, for example, from about 30 nm toabout 200 nm.

Referring to FIGS. 2A-2B, the semiconductor structure 100 is illustratedafter forming a trench 201 through the dielectric capping layer 130, thecapping spacer 111, the dummy gate 120, and the intermediate dielectricregion 20 (including the intermediate dielectric layer 112 andintermediate spacers 110 a/110 b) to expose the heavily-doped sourcelayer 103.

The trench 201 is formed by performing using multiple etching processes.For instance, a lithographical mask layer (not shown) may be formed atopthe dielectric capping layer 130 and patterned to define a desiredlocation and pattern of the trench 201. Thereafter, a first etchingprocess selective to the capping spacer 111 is performed to remove aportion of the dielectric capping layer 130 corresponding to the patternof the mask layer. A second etching process selective to the dummy gate120 is then performed to punch through the capping spacer 111.Accordingly, the upper surface of the dummy gate 120 can be exposed. Athird etching process selective to the upper intermediate spacer 110 bis then performed to extend the depth of the trench 201 through thedummy gate 120. Lastly, a fourth etching process selective to theheavily-doped source layer 103 is performed to punch through the lowerintermediate spacer 110 a. The resulting trench 201 therefore extendsthrough a top surface of the dielectric capping layer 130 and down tothe upper surface of the heavily-doped source layer 103. The width ofthe trench 201 may range, for example, from about 3 nm to about 20 nm.The depth of the trench 201 may range, for example, from about 50 nm toabout 300 nm.

FIGS. 3A-3B illustrate the semiconductor structure following anoxidation process that oxidizes a portion of the dummy gate 120. In atleast one embodiment, the oxidation process forms a thin oxide film 401along sidewalls of the dummy gate 120. The oxidation may be performed bya plasma oxidation process or other oxidation process that forms a thinoxide 401 layer. The lateral width (i.e., the distance along the X-axisdirection) of the oxide layer 401 may range, for example, from about 0.5nm to about 2 nm.

Turning to FIGS. 4A-4B, an epitaxial growth process is performed to fillthe trench 201 with a semiconductor material. In at least oneembodiment, the channel material is a doped semiconductor material thatis epitaxially grown from the heavily-doped source layer 103 to form theepitaxial channel 501, i.e., the channel region 501. The channel region501 extends vertically from the heavily-doped S/D layer 103 and fillsthe trench 201 so as to extend through the lower intermediate spacer 110a, the dummy gate 120, the upper intermediate spacer 110 b, and cappingspacer 111. The epitaxial growth includes an epitaxial semiconductormaterial, and the epitaxial growth and/or deposition processes areselective to a semiconductor surface and do not deposit material onother surfaces, such as the oxide layer 401, the intermediate spacers110 a-110 b or capping spacer 111. The epitaxial growth in the epitaxialchannel region 501 extends over the dielectric capping layer 130.

The material of the channel region 501 may be grown using a suitablegrowth process, for example, chemical vapor deposition (CVD), liquidphase (LP) or reduced pressure chemical vapor deposition (RPCVD),vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phaseepitaxy (LPE), metal organic chemical vapor deposition (MOCVD), or othersuitable processes.

Based on the epitaxial growth process described above, the channelregion 501 may comprise various materials including, but not limited to,silicon (Si), germanium (Ge), or a combination thereof (e.g., SiGe). Thegas source for the deposition of epitaxial semiconductor material mayinclude a silicon-containing gas source, a germanium-containing gassource, or a combination thereof. For example, an epitaxial siliconlayer may be deposited from a silicon gas source that is selected fromthe group consisting of silane, disilane, trisilane, tetrasilane,hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane,methylsilane, dimethylsilane, ethylsilane, methyldisilane,dimethyldisilane, hexamethyldisilane, and combinations thereof. Anepitaxial germanium layer can be deposited from a germanium gas sourcethat is selected from the group consisting of germane, digermane,halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, andcombinations thereof. An epitaxial silicon germanium alloy layer can beformed utilizing a combination of such gas sources. Carrier gases likehydrogen, nitrogen, helium and argon can be used.

Referring to FIGS. 5A-5B, the semiconductor structure 100 is illustratedafter partially recessing the material of the channel region 501, andre-filling the resulting trench with a dielectric material to form achannel cap 701. In at least one embodiment, the material of the channelregion 501 may be partially recessed to a level that is still within thedielectric capping layer 130 and above the capping spacer 111. Thematerial of the channel region 501 may be recessed, for example, using atimed reactive ion etching (RIE) process or a wet etch process. Itshould be appreciated that a planarization process may be performedafter depositing the channel cap dielectric material such that the uppersurface of the channel cap 701 is flush with the upper surface of thedielectric capping layer 130 as further illustrated in FIG. 5A.

The dielectric material of the channel cap 701 may comprise variousmaterials including, but not limited to, a dielectric oxide (e.g.,silicon oxide), a dielectric nitride (e.g., silicon nitride), adielectric oxynitride, or any combination thereof. The channel cap 701may be deposited using various deposition processes such as, forexample, chemical vapor deposition (CVD) or physical vapor deposition(PVD).

Turning to FIGS. 6A-6B the semiconductor structure 100 is illustratedafter performing an epitaxial growth process to grow an upper S/D region801 from the channel region 501. In at least one embodiment, the upperS/D region 801, which in this example serves as a drain region 801, hasa substantially smaller surface area than the heavily-doped lower S/Dregion 103, which in this example serves as the lower S/D region 103,which serves as a source of the FET. In at least one embodiment, theupper S/D region 801 may have a lateral width ranging, for example, fromapproximately 8 nm to approximately 30 nm, the lower S/D region 301 hasa much larger lateral width ranging from approximately 30 nm toapproximately 150.

The drain region 801 may be formed by first performing an etchingprocess selective to the capping spacer 111, the channel region 501 andthe channel cap 710. In this manner, a portion of the channel region 501located between the channel cap 710 and the capping spacer 111 isexposed. Next, an epitaxially growth process is performed that grows anepitaxial material 801 from sidewalls of the exposed channel region 501.Accordingly, the epitaxially grown material may serve as an upper S/Dregion 801, which in this non-limiting embodiment is a drain region 801.Accordingly, the channel region 501 extends vertically from theheavily-doped lower S/D region 103 (e.g., the source region 103) to theupper S/D region 801 (e.g., the drain region 801).

In at least one embodiment, a portion of the epitaxial channel 501located between the channel cap 701 and the capping spacer 111 may berecessed along sidewalls before epitaxially growing the drain region801. Although the epitaxially grown material 801 is discussed in termsof forming a drain region, it should be appreciated that the epitaxiallygrown material 801 may serve as a source region while the heavily-dopedS/D region 103 serves as the drain region. The epitaxy process used toform the drain region 801 may be carried out using various well-knowntechniques including, but not limited to, vapor phase epitaxy (VPE),molecular beam epitaxy (MBE) or liquid phase epitaxy (LPE) with agaseous or liquid precursor, such as, for example, silicontetrachloride.

Turning now to FIGS. 7A-7B, the semiconductor structure 100 isillustrated following a spacer deposition process that forms S/D spacers901 on an outer surface of the drain region 801 and channel cap 701. TheS/D spacers 901 may therefore serve to protect the drain region 801 whenperforming subsequent fabrication operations discussed in greater detailbelow.

The S/D spacers 901 comprise an insulating material including, but notlimited to, dielectric oxides (e.g., silicon oxide), dielectric nitrides(e.g., silicon nitride), dielectric oxynitrides, or any combinationthereof. The material of the spacers may be deposited using variousdeposition processes such as, for example, chemical vapor deposition(CVD) or physical vapor deposition (PVD). In at least one embodiment, asubsequent etching process selective to the channel cap material may beperformed. In this manner, the S/D spacers 901 may be recessed to exposethe upper surface of the channel cap 701. The S/D spacers 901 have alateral width (i.e., extending perpendicular to the Z-axis) ranging, forexample, from about 5 nm to about 50 nm.

With reference now to FIGS. 8A-8B, the semiconductor structure 100 isillustrated following a selective etching process that etches a portionof the capping spacer 111 and a portion of the dummy gate layer 120while stopping on an upper surface of the lower intermediate spacer 110b. Although not illustrated, a masking layer may be deposited on anupper surface of the S/D spacers 901 and the channel cap 701. In thismanner, one or more selective etching process such as, for example, oneor more RIE processes may be performed to etch portions of the cappingspacer 111 and the dummy gate so as to expose upper surface of the upperintermediate spacer 110 b as further illustrated in FIGS. 8A-8B. Bydeposing a mask (not shown) on the upper surface of the S/D spacers 901and the channel cap 701, portions of the dummy gate 120 remain arrangedon sidewalls of the channel region 501.

Turning to FIGS. 9A-9B, the semiconductor structure 100 is illustratedafter removing the remaining portions of the dummy gate 120. Theremaining portion of the dummy gate 120 are removed by performing alateral etching process that is selective to the material of the oxidesidewalls 401, the intermediate spacers 110 a-110 b and the S/D spacers901. Accordingly, the oxide sidewalls 401 are exposed. In at least oneembodiment, the dummy gate 120 may be removed using a wet etch process,for example, that includes hot ammonia.

Referring to FIG. 10, the semiconductor structure 100 is illustratedafter depositing a dielectric material 1201 and a work function metal1202. The dielectric material 1201 and the work function metal 1202 forma portion of the gate stack (metal gate) that replaces the dummy gate120. In at least one embodiment, the gate dielectric material 1201 maybe initially deposited to conform to the outer surfaces of the upperintermediate spacer 110 a, the channel region 501, the S/D spacers 901,and the upper surface of the channel cap 701. The work function metal1202 is then deposited on the dielectric material 1201, Accordingly, thedielectric material 1201 and work function metal 1202 are formed againstthe sidewalls of the channel 501 such that the dielectric material 1201is in direct contact with the channel region 501, and is interposedbetween the channel region 501 and the work function metal 1202.

The gate dielectric material(s) can be a dielectric material having adielectric constant greater than 3.9, 7.0, or 10.0. Non-limitingexamples of suitable materials for the gate dielectric material 1201include oxides, nitrides, oxynitrides, silicates (e.g., metalsilicates), aluminates, titanates, nitrides, or any combination thereof.Examples of high-k materials (with a dielectric constant greater than7.0) include, but are not limited to, metal oxides such as hafniumoxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanumoxide, lanthanum aluminum oxide, zirconium oxide, zirconium siliconoxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide,barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, and lead zinc niobate. The high-k material may further includedopants such as, for example, lanthanum and aluminum. The gatedielectric material 1201 layer may be formed by suitable depositionprocesses, for example, chemical vapor deposition (CVD), plasma-enhancedchemical vapor deposition (PECVD), atomic layer deposition (ALD),evaporation, physical vapor deposition (PVD), chemical solutiondeposition, or other like processes. The thickness of the gatedielectric material 1201 may vary depending on the deposition process aswell as the composition and number of high-k dielectric materials used.

The material composition of the work function metal(s) 1202 may be basedon the type of semiconductor device (e.g., transistor) to be formed.Non-limiting examples of suitable work function metals 1202 includep-type work function metal materials and n-type work function metalmaterials. P-type work function materials include compositions such asruthenium, palladium, platinum, cobalt, nickel, and conductive metaloxides, or any combination thereof. N-type metal materials includecompositions such as hafnium, zirconium, titanium, tantalum, aluminum,metal carbides (e.g., hafnium carbide, zirconium carbide, titaniumcarbide, and aluminum carbide), aluminides, or any combination thereof.The work function metal(s) 1202 may be deposited by a suitabledeposition process, for example, CVD, PECVD, PVD, plating, thermal ore-beam evaporation, and sputtering.

In at least one embodiment, the gate dielectric material 1201 and workfunction metal 1202 may be partially removed to re-expose the S/Dspacers 901 as further illustrated in FIG. 10. An anisotropic etch maybe performed to remove the gate dielectric material 1201 and the workfunction metal 1202 from surfaces of the S/D spacer 901 and dielectricmaterial 1201. In at least one embodiment, the anisotropic etch may be,for example, a RIE process. After etching, the gate dielectric material1201 and work function metal 1202 located between the heavily-dopedsource layer 103 and the drain region 801. In at least one embodiment,the gate dielectric material 1201 and work function metal 1202 isconfined between the drain region 801 and the upper intermediate spacer110 b.

With reference to FIG. 11, the semiconductor structure 100 isillustrated after depositing a metal gate material 1501 thatencapsulates a portion of the channel region 501 lined with the gatedielectric material 1201 and the work function metal 1202. In at leastone embodiment, the metal gate contact material 1501 is blanketdeposited on the upper surface of the work function metal 1202 to coverthe S/D sidewalls 901 and the channel cap 701. Thereafter, the metalgate contact material 1501 is recessed until reaching the gatedielectric material 1201 and the work function metal 1202 as illustratedin FIG. 11.

The metal gate material 1501 is a conductive gate metal that isdeposited over the gate dielectric material(s) 1201 and work functionmetals 1202 to form the gate stack. Non-limiting examples of suitableconductive metals include aluminum (Al), platinum (Pt), gold (Au),tungsten (W), titanium (Ti), or any combination thereof. The conductivemetal may be deposited by a suitable deposition process, for example,CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering.

Turning now to FIG. 12, the semiconductor structure 100 is illustratedfollowing a gate lithography and etching process that forms a metal gate2501 and exposes an upper surface of the upper intermediate spacer layer110 b. In at least one embodiment, a mask (not shown) may be disposed onthe metal gate material 1501 and subsequently patterned. The pattern istransferred into the metal gate material 1501 to define the final metalgate 2501. In addition, the gate dielectric material 1201 and workfunction metal 1202 may also be etched during this operation using acombination of RIE processes. As further illustrated in FIG. 12, aportion of the lower intermediate spacer 110 a is formed between themetal gate 2501 and the heavily-doped source layer 103. It should beappreciated that the combination of the metal gate contact 501, the gatedielectric material(s) 1201, and the work function metals 1202 maydefine a metal gate structure (i.e., metal gate stack) which replacesthe dummy gate 120 and is arranged in contact with the channel region501.

Referring to FIG. 13, the semiconductor device 100 is illustratedfollowing deposition of an inter-layer dielectric (ILD) material 1730 onan upper surface of the upper intermediate spacer layer 110 b tosurround the metal gate stack (i.e., the metal gate contact) 501, themetal the gate dielectric material(s) 1201 and work function metals1202) and the S/D spacers 901. The ILD material 1730 may be formed from,for example, a low-k dielectric material (with k<4.0), including but notlimited to, silicon oxide, spin-on-glass, a flowable oxide, a highdensity plasma oxide, borophosphosilicate glass (BPSG), or anycombination thereof. The ILD material 1730 is deposited by a depositionprocess, including, but not limited to CVD, PVD, plasma enhanced CVD,atomic layer deposition (ALD), evaporation, chemical solutiondeposition, or like processes.

With reference now to FIG. 14, a lithography and patterning process isperformed to form a first contact trench 1000 a (e.g., a first S/Dtrench 1000 a) that extends through both the ILD material 1730 and theupper intermediate spacer layer 110 b, and into the intermediatedielectric layer 120. According to at least one embodiment, a resist,such as a photoresist, may be deposited and patterned to remove the ILD1730 and form the first S/D trench.

Turning now to FIG. 15, the semiconductor device 100 is illustratedfollowing a selective etching process to selectively remove theintermediate dielectric layer 120. In at least one embodiment, anetching process may be performed which selectively attacks theintermediate dielectric layer 120 while preserving the materials of theremaining semiconductor device 100. Accordingly, a void 1100 is formedin the semiconductor structure 100 which exposes a portion of thechannel region 501. With respect to the channel cap 701, the dielectricmaterial of the intermediate dielectric layer 120 may comprise a firstdielectric material while the channel cap 701 comprises a seconddielectric material different form the first dielectric material. Aftercompleting the selective etching process, the portion of the channelregion 501 located between the lower and upper intermediate spacers 110a-110 b is exposed as further illustrated in FIG. 15.

In at least one embodiment, the intermediate dielectric layer 120 andthe channel cap 701 may comprise the same dielectric material. In thiscase, a mask layer (not shown) may be deposited over the channel cap701. In this manner, the channel cap 701 may be protected whileselectively etching the intermediate dielectric layer 120 with respectto (i.e., while maintaining) the remaining materials of thesemiconductor structure 100.

Referring to FIG. 16, the semiconductor structure 100 is illustratedfollowing a selective etching process that removes the exposed portionof the channel region with respect to (i.e., while maintaining) thelower and upper intermediate spacers 110 a-110 b. In at least oneembodiment, a wet etch process selective to the material of the channelregion 501 (e.g., an epitaxially grown semiconductor material) isperformed. In this manner, a first remaining channel portion 503 a(e.g., a lower remaining channel portion 503 a) is partially surroundedby the lower intermediate spacer 110 a while a second remaining channelportion 503 b (e.g., an upper remaining channel portion 503 b) ispartially surrounded by the upper intermediate spacer 110 b as furtherillustrated in FIG. 16.

With reference now to FIG. 17, the semiconductor structure 100 isillustrated following a channel sigma etching process. In at least oneembodiment, the channel sigma etching process includes a wet etch suchas Tetramethylammonium hydroxide (TMAH), for example, which self-limitsto a point so as to form self-limiting cavities (e.g., v-grooves) in thechannel region and the heavily-doped S/D layer. The sigma etchingprocesses more aggressively material in the <111> facet-plane withrespect to material in the <110> facet-plane. In this manner, etchingdepth into the channel region 501 may be more precisely controlled.

For instance, the sigma etch applied to the lower remaining channelportion 503 a self-limits to form a lower v-groove 1600 a that extendsfrom an upper portion of the lower intermediate spacer 110 a into theheavily-doped source layer 103, while the sigma etch applied to theupper remaining channel portion 503 b self-limits (i.e.,self-terminates) to form an upper v-groove 1600 b that extends from thesurface of the upper intermediate spacer 110 b into the remainingchannel region 501 as further illustrated in FIG. 17. The self-limitingdepth of the lower and upper v-grooves 1600 a-1600 b are controlled bythe lateral width of the initial channel region 501. For instance, alarger channel region width correlates to a larger self-limiting depth.In at least one embodiment, the vertical width of the upper intermediatespacer 110 b may control the depth of the upper v-groove 1600 b. Thedepth of lower v-groove 1600 a may range, for example, fromapproximately 4 nm to approximately 15 nm, and the depth of upperv-groove 1600 b may range, for example, from approximately 4 nm toapproximately 15 nm. In at least one embodiment, the v-grove is etched,for example, using hydrogen chloride (HCl) or Ammonia (NH₃).

Turning to FIG. 18, the semiconductor structure 100 is illustrated afterforming a stressor region 1800 between the channel region 501 and theheavily-doped source layer 103. The stressor region 1800 induces astrain (e.g., compressive or tensile) on the channel region 501. Thatis, semiconductor material of the stressor region 1800 has a latticeconstant that is different from the lattice constant of the channelregion 501 so as to induce a strain on the channel region. By strainingthe channel region 501, hole or electron mobility through the channelregion 501 may be improved.

As described above, the stressor region 1800 fills both the lowerv-groove (previously indicated as 1600 a) and the upper v-groove(previously indicated as 1600 b). Accordingly, the stressor region 1800includes a lower v-shaped end 1802 a that extends into the heavily-dopedlayer 103 and an upper v-shaped end 1802 b that extends into the channelregion 501. In this manner, the combination of the remaining channelregion 501 and the stressor region 1800 defines the total length of astrained channel region of the semiconductor structure 100 (e.g.,vertical field effect transistor).

In at least one non-limiting embodiment, the stressor region 1800 isformed by epitaxially growing a strain-inducing material from theheavily-doped source layer 103 exposed by the lower v-groove 1600 a andfrom the channel region 501 exposed by the upper v-groove 1600 b. Thestrain-inducing material includes a doped semiconductor material havinga lattice constant different form the lattice constant of the channelregion 501. When fabricating a p-FET device, for example, the channelregion 501 may comprise Si, while the strain-inducing material comprisesdoped silicon germanium (SiGe) to induce a compressive strain on thechannel region 501. When fabricating a n-FET device, for example, thechannel region 501 may comprises Si, while the strain-inducing materialcomprises doped carbon doped silicon (Si:C) to induce a tensile strainon the channel region 501. The germanium concentration (e.g., atomicconcentration) can range from 20% to 85% in the silico-germanium. Thecarbon concentration (atomic concentration) can range from 0.5% to 2.5%in the Si:C.

In another embodiment, the stressor region 1800 is formed by performingan atomic layer deposition (ALD) process to deposit the dopedstrain-inducing material to file the lower and upper v-grooves 1600a-1600 b. After the doped strain-inducing material is deposited, ananneal process may be performed to induce the strain upon the channelregion 501.

With reference to FIG. 19, the void (previously indicated as element1100) is filled with a second ILD layer 1740. Accordingly, the secondILD layer 1740 is deposited between the lower and upper intermediatespacers 110 a-110 b to encapsulate the stressor region 1800. The ILDlayer 1740 may comprise a low-k dielectric material (with k<4.0),including but not limited to, silicon oxide, spin-on-glass, a flowableoxide, a high density plasma oxide, borophosphosilicate glass (BPSG), orany combination thereof. Various deposition processes may be used toapply the second ILD layer 1740 including, but not limited to CVD, PVD,plasma enhanced CVD, atomic layer deposition (ALD), evaporation,chemical solution deposition, or like processes.

After depositing the second ILD layer, 1740 a lithography and patterningprocess is performed to form contact trenches as further illustrated inFIG. 19. The contact trenches serve to define the dimensions of metalcontact vias which are described in greater detail below. Formation ofthe contact trenches includes extending the depth of the first S/Dtrench 1000 a into the heavily-doped source layer 103. In at least oneembodiment, a single timed etch may be used to extend the first S/Dtrench 1000 a through the second ILD layer 1740 and the lowerintermediate spacer 110 a to expose the heavily-doped source layer 103.Alternatively, a first etching processes selective to a spacer materialmay be used first etch through the second ILD layer 1740 while a secondetching process selective to a semiconductor material may be used topunch through the lower intermediate spacer 110 a. Thereafter, a timedetching process may be used to extend the first S/D trench 1000 a intothe heavily-doped source layer 103.

Still referring to FIG. 19, a second contact trench 1000 b (e.g., a gatetrench 1000 b) and a third contact trench 1000 c (e.g., a second S/Dtrench 1000 c) are also formed. The gate trench 1000 b extends throughthe first ILD material 1730 and into a metal gate structure metal gate2501. The second S/D trench 1000 c is formed in between the S/D spacers901 so as to expose the drain region 801. The gate trench 1000 b and thesecond S/D trench 1000 c may be formed using similar proceduresdescribed above with respect to the first S/D trench 1000 a.

Turning to FIG. 20, the semiconductor structure 100 is illustrated afterfilling the first S/D trench 1000 a, the gate trench 1000 b and thesecond S/D trench 1000 c with a metal material form a first S/D metalcontact via 1002 a, a gate metal contact via 1002 b, and a second S/Dmetal contact via 1002 c. The trenches (previously shown as elements1000 a-1000 c) may be filled with a conductive material or a combinationof conductive materials. The conductive material may be a conductivemetal, for example, aluminum (Al), platinum (Pt), gold (Au), tungsten(W), titanium (Ti), or any combination thereof. The conductive materialmay be deposited by a suitable deposition process, for example, CVD,PECVD, PVD, plating, thermal or e-beam evaporation, or sputtering. Aplanarization process, for example, CMP, may be performed to remove anyconductive material from the surface of the first ILD 1730 and the S/Dspacers 901.

Accordingly, various embodiments provide a semiconductor device thatincludes a stressor region having a different lattice constant comparedto the channel region material. The stressor region induces a strainupon the channel region thereby providing a vertical FET havingimproving hole (or electron) mobility. In at least one embodiment, asigma-etching process is utilized to form a self-limiting v-groove inthe channel region near the bottom terminal of the vertical FET. Theself-limiting v-groove assists in reducing the variations seen inconventional vertical FET fabrication processes. In addition, theself-limiting v-groove precisely controls the depth at which thestressor region extends into the channel region.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed is:
 1. A method of inducing strain on a channel regionof a vertical transistor, the method comprising: forming a channelregion that extends from a first source/drain region to a secondsource/drain region; encapsulating a first portion of the channel regionwith a first encapsulating structure and a second portion of the channelregion with a second encapsulating structure; removing the secondencapsulating structure while maintaining the first encapsulatingstructure to expose the second portion of the channel region; andreplacing the second portion of the channel region with a stressorregion that induces a strain on the first portion of the channel region.2. The method of claim 1, wherein the first encapsulating structure is ametal gate structure and the second encapsulating structure is aninter-layer dielectric (ILD) material, and wherein removing the secondencapsulating structure includes selectively etching the secondencapsulating structure while maintaining the second portion of thechannel region.
 3. The method of claim 1, wherein replacing the secondportion of the channel region includes: selectively etching the secondportion of the channel region, the second portion extending from firstsource/drain region to the first portion of the channel region;performing a sigma etching process that forms a first v-shaped groove inthe first source/drain region and a second v-shaped groove in the firstchannel region; and forming the stressor region having a first end thatcontacts the first source/drain region and a second end that contactsthe first portion of the channel region.
 4. The method of claim 3,wherein a width of the channel region controls a depth of the first andsecond v-shaped grooves self-terminates.
 5. The method of claim 3,wherein forming the stressor region includes epitaxially growing a dopedsemiconductor material from the first source/drain region exposed by thefirst v-shaped groove and from the first portion of the channel regionexposed by the second v-shaped groove, the doped semiconductor materialhaving a lattice constant that is different from a lattice constant ofthe first portion of the channel region.
 6. The method of claim 3,wherein forming the stressor region includes: performing an atomic layerdeposition process so as to deposit a doped semiconductor materialextending from the first source/drain region exposed by the firstv-shaped groove to the first portion of the channel region exposed bythe second v-shaped groove; and performing an anneal process so as toactivate dopants in the semiconductor material such that a latticeconstant of the stressor region is different from a lattice constant ofthe first channel portion.
 7. The method of claim 5, wherein the firstportion of the channel region comprises silicon (Si) and the dopedsemiconductor material of the stressor region comprises silicongermanium (SiGe) so as to induce a compressive strain on the channelregion.
 8. The method of claim 5, wherein the first portion of thechannel region comprises silicon (Si) and the doped semiconductormaterial of the stressor region comprises carbon doped silicon (Si:C) soas to induce a tensile strain on the channel region.
 9. A method ofinducing a strain on a channel region of a vertical field effecttransistor (FET), the method comprising: removing an encapsulatingstructure to form a void that exposes a first portion of the channelregion, the channel region having a first lattice constant; selectivelyremoving the first portion of the channel region while preserving asecond portion of the channel region, the second portion having a firstchannel end connected to a first source/drain region and a secondchannel end exposed to the void; and forming a stressor region having afirst stressor end formed against the second channel and a secondstressor end formed against a second source/drain region, the stressorregion having a second lattice constant different from the first latticeconstant so as to induce a strain on the preserved second portion of thechannel region.
 10. The method of claim 8, wherein the encapsulatingstructure is a metal gate structure, and wherein selectively removingthe first portion of the channel region includes performing a sigma etchto form a first v-shaped groove that extends into the preserved secondportion of the channel region.
 11. The method of claim 9, wherein awidth of the channel region controls a depth of the first and secondv-shaped grooves self-terminates.
 12. The method of claim 9, whereinforming the stressor region includes epitaxially growing a dopedsemiconductor material from the preserved second portion exposed by thev-shaped groove.
 13. The method of claim 9, wherein forming the stressorregion includes performing an atomic layer deposition process to deposita doped semiconductor material in the first v-shaped groove so as tocontact the preserved second portion of the channel region; andperforming a thermal anneal process so as to activate the dopedsemiconductor material.
 14. The method of claim 9, wherein the preservedsecond portion of the channel region comprises silicon (Si) and thedoped semiconductor material of the stressor region comprises silicongermanium (SiGe) so as to induce a compressive strain on the channelregion.
 15. The method of claim 9, wherein the preserved second portionof the channel region comprises silicon (Si) and the doped semiconductormaterial of the stressor region comprises carbon doped silicon (Si:C) soas to induce a tensile strain on the channel region.